# Clocking A and N in a Dual-modulus PLL Prescaler

In an effort to "up my game" attempting to build a VFO for my DIY transceiver, I've been looking at PLL theory and circuits. Many of my research references are quite old and I understand that many of the concepts I'll talk about here are no longer popular and have been replaced by integrated solutions and DDS. So, this question is about "How did they do that?" and "How might you do that nowadays?"

More specifically, many of the PLL circuits for high frequency VFOs would use some kind of dual-modulus prescaler to divide down the VFO frequency before the phase comparator. The wikipedia link offers a fair description of how these "fractional-N" type prescalers work and I'm speaking about the discrete ICs - not the ones integrated into the PLL itself.

Lets take the MB501 used in the wikipedia article. This IC is just about still available (if you look hard enough!) and has a nice lower end frequency of 10MHz (many currently available ICs have much higher lower end frequencies). It looks to me that to use this IC for fractional division, you'll need additional A and N counters. If you take the example given in wikipedia, it seems like those additional counters will need to operate at over 7MHz (918MHz / 128). That figure would be higher if you chose a lower M or had a higher VFO frequency. My point is, the clock frequency might be on the high side for a uP or discrete counting logic. So, how did they implement the A and N counters for this solution?

As an additional "bonus" question, if someone more familiar with this stuff than I am were to build a PLL circuit in the spirit of the more discrete designs (i.e., basic PLL, maybe 4046 with separate prescaler), how would you go about it?

UPDATE: a bit more research seems to show that discrete prescalers like the MB501 were driven by the PLL ICs themselves. Not all PLL ICs had this capability. Seems that you programmed a N and A into the PLL and it did the counting for you. I suppose that makes some sense, since it's the output of the N divider that gets presented to the phase comparator. Anyway, I'm guessing (hoping?) someone out there has done this with a less specialized PLL, like the 4046.