I/Q demodulation of DSBSC-AM signals

Question

I was looking at some Stereo FM demodulators on the Internet, and I can't understand the use of the complex to real block for demodulation of the L-R signal (DSBSC-AM) which can be seen in different projects, for example:

1. https://github.com/gnuradio/gnuradio/blob/master/gr-analog/python/analog/wfm_rcv_pll.py#L145-L147
2. https://github.com/vsergeev/luaradio/blob/master/radio/composites/wbfmstereodemodulator.lua#L36-L39

My (possibly flawed) understanding is that complex to real can be used here only because in both cases there is a PLL which accurately tracks the phase. Is this correct? Because I also explored the gr-rds project, and I can't understand how it works without a PLL block. There were PLL blocks until this commit but they were removed. Another example is the luaradio SSB demodulator which again uses complex to real without some type of carrier recovery.

So, my question is: what is the right way to demodulate a DSBSC-AM signal (with and without a pilot tone) and how is the complex to real (not complex to magnitude) block able to do it, even without a PLL in the rds_rx flowgraph?

Answer 1

The code is too complex for the time that I have available. Since nobody reacts: probably this can help you to understand what I think is realised in the code.

Your assumption that the phase of the recovered carrier must be unique and related to the phase of the pilot tone is correct. A zero crossing of the 19 kHz pilot tone must correspond to a zero crossing of the 38 kHz (the reverse is not, because there are more zero crossings in 38 kHz recovered carrier). Observed as time division multiplex signal: after a zero crossing of the 19 kHz first there is the left channel audio signal and then, 90 degrees later in the 19 kHz signal, there is the right hand channel audio signal; up to 180 degrees phase of the 19 kHz pilot. And so on, that alternating left/right.

To come back to your question: it is not necessary to make that analog PLL for subcarrier 38 kHz synchronous detection in the digital domain. With a complex multiplier or a CORDIC it is possible to multiply a DSP-clock frequency of about 19 kHz, not exactly but close, multiply estimated (generated) 19 kHz with the pilot tone, and filter the output low-pass (this error signal is the offset frequency between the two systems) and construct the wanted 38 kHz with correct frequency and phase. This is a feed-forward system without locking. The figure attached is easier to understand than my words. PA0FSB Copyright for the document: I am the source.