Will the quantization noise be increased if the step level is increased? I was wondering about the relationship between the step size of the quantizer and quantization noise,


Quantization noise is highly dependent on the signal source distribution and its amplitude, the number of ADC bits, and the use of dithering.

For a high resolution ADC that is digitizing a full amplitude sine wave, the maximum noise contribution is:

$$\text{SNQR}_\text{dB}=1.76+Q \cdot 6.02 \tag 1$$

where $Q$ is the number of bits.

Here we can observe that increasing the number of bits increases the maximum SNQR by the 6.02 dB factor per bit. The 1.76 term simply accounts for the non-uniform distribution of the sine wave.

The origin of formula 1 is found in the formula for ideal noise contribution of the lower +/- 1/2 bit:

$$\text{SNQR}_\text{dB}=20\log_{10}(2^Q) \tag 2$$

Formula 1 generally remains true for complex signals being quantized by high resolution ADCs. Lower level signal inputs or low bit ADCs will generally suffer from a higher noise contribution (lower SNQR) unless appropriate counter measures are deployed.


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