One of the earlier SDR models, the HPSDR, had/has a single receive board: the "Mercury". It used a single high speed ADC. Details are here.
Once the RF if sampled and fed into an FPGA, it typically gets split into I and Q streams anyway. If you have a 120Msps ADC, for example, you could mix with a 30MHz SINE signal (0, 1, 0, -1, repeat) and a 30MHz COSINE signal (1, 0, -1, 0, repeat).
Benefits? Well for starters, you've halved the number of ADC's and associated amps, physical filters, etc. You still have them - but now they need to be implemented In Code in the FPGA. Seperate I and Q channels also tend to have distortion problems around DC.
Drawbacks? You have to wite more code. Some of that code (the complex exponential) can be quite hard to do well. Edit: Another expense-related problem: your single ADC now has to be twice as fast. This can significantly impact ADC Cost, and even the circuit design.
As for your idea of looking at 100 - 150MHz: this is where oversampling comes in. If you sample a 60MHz signal with a 100MHz ADC, the Nyquist effect makes it "look like" a 40MHz signal, ie. reflected around the half-sample rate. A 90MHz signal will "look like" a 10 MHz signal. What would a 101 MHz signal look like...?
It would look like a 1 MHz signal. This is oversampling.
Looking at a bandwidth of (up to) half the sample rate, while technically possible, is pushing things a bit. In practice, for the conditions you specified, I'd use ADC's rated at 160Msps (or higher), and expect data between 60 - 10MHz. Such ADC's don't come cheap, so I'd probably consider a single ADC version to start with.
Also note how the frequency band got "reversed" by using the Nyquist oversampling. This can impact decoding analog TV (color burst in wrong location), SSB (LSB becomes USB), and commercial FM (stereo information in secondary signal).